Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, flash drives, digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
A typical flash memory device is a type of memory in which the array of memory cells is typically organized into memory blocks that can be erased and reprogrammed on block-by-block basis instead of one byte at a time. Changes in a threshold voltage of each of the memory cells, through erasing or programming of a charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. The data in a cell of this type is determined by the presence or absence of the charge in the charge storage structure.
A three dimensional memory device uses stacked memory arrays on a single die. Such a memory architecture allows higher memory density in substantially the same die footprint. FIG. 1 illustrates one example of the architecture of a typical prior art stacked NAND flash memory array.
The embodiment of FIG. 1 shows a two layer 100, 101 stacked architecture. Both layers 100, 101 share the same source line 103, access lines (e.g., word lines) 105-107, and select gate source lines 110. Each layer 100, 101 is selected by the data line (e.g., bit line) 120, 121 bias. In the illustrated example, the bottom layer array 101 is coupled to bit line BL0 120 and the top layer array 100 is coupled to bit line BL1 121.
FIGS. 2A-2C show diagrams of voltages for typical prior art memory operations (e.g., programming FIG. 2A, sense FIG. 2B, and erase FIG. 2C) that can be executed in a stacked memory array architecture. To better illustrate the operations, a four layer architecture is assumed.
The programming operation includes applying a programming voltage (e.g., 20V) to the selected word lines 201 being programmed. Since a word line is shared by all layers, bit line biasing (e.g., applying a bit line voltage) is used to inhibit layers that are not selected for programming. In the illustrated example, the first and third layers are selected to be programmed so their respective bit lines are biased at an enable voltage (e.g., 0V) while the unselected bit lines are biased at an inhibit voltage (e.g., 2V). Thus, the first and third layers are selected while the second and fourth layers are unselected.
For erase and sense operations, all of the layers can be selected substantially simultaneously while, in the sense operation, only one row of each layer is selected. For example, during a sense operation, all of the bit lines are biased at a lower voltage (e.g., 0.5V) while the read voltage (Vr) is applied to the common word line 202. The unselected word lines are biased at some pass voltage Vpass (e.g., 6V), the select gate lines are turned on (e.g., 5V).
During an erase operation, all of the bit lines are biased at a relatively large erase voltage (e.g., 20V) while all of the word lines are biased at a reference voltage (e.g., 0V). The select gate drain lines and common select gate source lines are biased with a relatively large voltage (e.g., 20V).
One problem with programming in a stacked memory array architecture is the programming disturb that can occur due to a programming rate offset between layers. For example, referring to FIG. 2A, if the first layer programs at a slower rate than the fourth layer, the relatively large voltages applied to the slower first layer in order to continue programming the first layer for a longer time than the faster fourth layer can cause programming stress to the fourth layer. Such disturb can cause errors during sense operations since the memory cell threshold voltages on the disturbed layer can be increased from the originally programmed voltage levels.
For the reasons stated above and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for reducing the effects of program disturb.